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Timing Verification in Transaction Modeling

Timing Verification in Transaction Modeling

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Hardware/Software (Hw/Sw) systems are likely to become essential in all aspects of everyday life. However, the productive design of these systems is limited by several factors, some of them being the increasing complexity of applications, the heterogeneous nature of products and services as well as the shrinking of the time-to-market delay. Transaction Level Modeling (TLM) paradigm is considered as one of the most promising simulation paradigms to break down the design complexity by allowing the exploration and validation of design alternatives at high levels of abstraction. This research proposes a timing expression methodology in Transation Level Models based on temporal constraints analysis. We propose to use a combination of two paradigms to accelerate the design process: TLM on one hand and a methodology to express timing between different transactions on the other hand. As there are many definitions of TLM with several pro and contra, in the context of our research we define a hardware/software (Hw/Sw) specification and simulation methodology which supports TLM in such a way that several modeling concepts can be seen separately.
Timing Verification in Transaction Modeling